ECCDIS=ECCDIS_0, SIWT=SIWT_0, FORCEWT=FORCEWT_0
L1 Cache Control Register
| SIWT | Shared cacheable-is-WT for data cache. Enables limited cache coherency usage. 0 (SIWT_0): Normal Cacheable Shared locations are treated as being Non-cacheable. Default mode of operation for Shared memory. 1 (SIWT_1): Normal Cacheable shared locations are treated as Write-Through. |
| ECCDIS | Enables ECC in the instruction and data cache. 0 (ECCDIS_0): Enables ECC in the instruction and data cache. 1 (ECCDIS_1): Disables ECC in the instruction and data cache. |
| FORCEWT | Enables Force Write-Through in the data cache. 0 (FORCEWT_0): Disables Force Write-Through. 1 (FORCEWT_1): Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through. |